Keynote Speeches and Plenary Talk

Program at Glance

Enrico Macii has research interests in the design automation of digital circuits and systems. He has authored over 330 publications in this area, including the book: “Ultra Low-Power Electronics and Design” by Kluwer. He received the Best Paper Award for articles presented at IEEE EURODAC-96 and at ACM/IEEE GLS-VLSI-08.

Since 2006, Enrico Macii is the Editor-in-Chief of the IEEE Transactions on CAD. Prior to that, he was an Associate Editor for the same journal (1997-2005) and an Associate Editor for the ACM Transactions on Design Automation (2000-2005). He was the Guest Editor of a Special Issue of IEEE Design and Test (2000), the Guest Co-Editor of a Special Issue of the IEEE Transactions on VLSI Systems (2001), and the Guest Co-Editor of a Special Issue of the IEE Proceedings (2002).

Enrico Macii was the Technical Program Co-Chair (1999) of the IEEE Alessandro Volta Memorial Workshop on Low Power Design, the Technical Program Co-Chair (2000) and the General Chair (2001) of the ACM/IEEE ISLPED, the General Chair (2003) and the Technical Program Chair (2004) of the IEEE PATMOS, the General Co-Chair (2007) and the Technical Program Co-Chair (2008) of the ACM/IEEE GLS-VLSI. Currently, he is the Vice Program Chair of the IEEE DATE Conference (2009).

Enrico Macii is involved in several industry-oriented research projects, including cooperations with Accent, ARM, Freescale, Hewlett-Packard, Intel, Intracom, Philips, Siemens, STMicroelectronics and Synopsys. He is one of the co-founders and the Chief Technology Advisor of BullDAST s.r.l., a start-up company operating in the field of EDA services and tools for low power design.. He was the Technical Manager for Politecnico di Torino of ESPRIT project n. 26796 (PEOPLE: Power Estimation for Fast Exploration of Embedded Systems), of FP5 IST projects IST-2000-30093 (EASY: Energy-Aware System-on-Chip Design of the Hiperlan/2 Standard), IST-2000-30125 (POET: Power Optimization of Embedded Systems), IST-2001-37115 (MARLOW: A Central Market-Place for Dissemination of Low-Power Microelectronics Design Knowledge), of FP6 IST project IST-4-026980-IP (CLEAN: Controlling Leakage Power in NanoCMOS SoCs), of FP6 CRAFT project SME-2004-COOP-031984 (MAP2: Micro-Architectural Power management: Methods, Algorithms and Prototype tools), and the Project Coordinator of IST project IST-2001-34631 (INTRALED: Industry-Driven Training for Low-Power European Designers). Currently, he is the Technical Manager for Politecnico di Torino of the ENIAC project MODERN and of the ARTEMIS project SCALOPES. He was an Evaluator of proposals and a Reviewer of projects on behalf of the European Commission in the context of FP5 and FP6.

Enrico Macii is a Fellow of the IEEE. He was an Elected Member of the Board of Governors of the IEEE Circuits and Systems Society for two consecutive terms of duty (2002-2004 and 2005-2007). Currently, he is the Vice President for publications of the IEEE Circuits and Systems Society and he is a Member of the Board of Governors of the IEEE Council on Electronic Design Automation (term ending in December 2009).

Abstract: Increase in chip power density results in higher operating temperatures, and thermal gradients (spatial and temporal) arise due to areas of the die with different power consumption. Thermal variations affect normal operation of nanoelectronic circuits in various dimensions, including reliability, leakage power and delay. And the picture will get more complicated (possibly worse) for CMOS devices with feature size below 45nm. This talk provides an overview of some of the most recent design and synthesis techniques that will help in reducing the run-time temperature, as well as governing the effects of on-chip thermal gradients in the future generations of CMOS integrated circuits.

Chang Wen Chen is an Empire Innovation Professor of Computer Science and Engineering at the State University of New York at Buffalo . Previously, he has been Allen Henry Endow Chair Professor of Electrical and Computer Engineering at the Florida Institute of Technology from 2003 to 2007. He was on the faculty of Electrical Engineering Dept. at the University of Rochester from 1992 to 1996, on the faculty of Electrical and Computer Engineering Dept at the University of Missouri-Columbia from 1996 to 2003. He also served as the Head of Interactive Media Group at David Sarnoff Research Labs in Princeton from 2000 to 2002, managing numerous research projects in video coding standards and wireless video communications.

Currently, he is the Editor-in-Chief for IEEE Trans. Circuits and Systems for Video Technology . He has been an Editor for numerous IEEE Transactions and Journals, including Proceedings of IEEE, IEEE Journal of Selected Areas in Communications, IEEE Trans. on Multimedia, and IEEE Multimedia Magazine. He has also served as Conference Chair for several major IEEE and SPIE conferences related to mobile wireless video communications and signal processing. His current research interests include reliable and secure multimedia communications over mobile wireless channels; digital video coding, processing, analysis, and embedded implementation; medical image analysis and biomedical information processing; distributed source coding and digital signal processing for communications; and collaborative signal processing and data aggregation for wireless sensor networks. His research is supported by NSF, DARPA, Air Force, NASA, Whitaker Foundation, Kodak, Cisco, and Huawei. He has received several Best Paper Awards from both IEEE and SPIE.

He received his BS from University of Science and Technology of China in 1983, MSEE from University of Southern California in 1986, and Ph.D. from University of Illinois at Urbana-Champaign in 1992. He was elected an IEEE Fellow for his contributions in digital image and video processing, analysis, and communications, and elected an SPIE Fellow for his contributions in electronic imaging and visual communications.

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Tor Sverre Lande is a professor in the Microelectronic/nanoelectronics at Dept. of Informatics, Univ. of Oslo. From 2004-2007 he is also served as visiting professor at Institute of Biomedical Engineering, Imperial College, London, UK.

His primary research is related to microelectronics, both digital and analog. Research fields are Neuromorphic Engineering, analog signal processing, micropower circuit and system design, biomedical circuits and systems and impulse radio (UWB). He is the author or co-author of more than 90 scientific publications with chapters in two books.

He is currently serving as an Associate Editor of several scientific journals. He has served as Guest Editor of special issues like IEEE Transactions on Circuits and Systems, vol II, special issue on “Floating gate Circuits and Systems”, Jan 2001 and IEEE Transactions on Circuits and Systems, vol I, special issue on “Biomedical Circuits and Systems”.

He is/has been a technical committee member of several international conferences and has served as reviewer for a number of international technical journals. He has served as Technical Program Chair for several international conferences (ISCAS 2003 in Bangkok, NORCHIP 2004 in Oslo, BioCAS workshop 2004 in Singapore, BioCAS 2006 in UK). He was the Chair Elect (2003-2005) of the IEEE Biomedical Circuits and Systems Technical Committee (BioCAS) and is also member of other CAS technical committees.

In 2006 he was appointed Distinguished Lecturer of the IEEE Circuits and Systems Society (CAS) and elected member of CAS Board of Governors. He is also serving as the first Editor-in-Chief of the new IEEE Transactions on Biomedical Circuits and Systems . In 2006 he was appointed Senior Member of the IEEE.

Abstract: We are still climbing on the amazing evolution of microelectronics (or maybe nanoelectronics) predicted by Gordon More in the sixties. The simple and well proven digital design paradigm combined with technology improvements has given us very compact computational systems. Combined with wireless technology, microelectronics systems are appearing not only in mobile phones, but all around us and even inside our body. We are getting more for less, not only more for less money, but less power, smaller size and more devices… With billions of transistors to play with, what more can we ask for as designers? Are we approaching some saturation limit of manageable devices of a silicon system?

In order to understand technological challenges, we need to figure out where we are heading. The “boxed” digital systems as we know it from PCs are designed for interaction with humans and are matured to a fantastic tool. However, microelectronics is spreading out around us interacting directly with the analog world, sensing and controlling our environment. Unlike PCs these systems are small, battery-operated and autonomous with wireless connectivity. A popular organizational structure is wireless sensor networks (WSN) with dynamic network structure and robust communication links. On these computational WSN nodes or motes we need to add sensors and actuators and even wireless connectivity, everything powered with a small battery. As always, as much as possible of mote functionality must be integrated on a single chip (System-on-Chip) including sensors/analog interfaces and wireless connectivity. Designing WSN motes is profoundly different from designing a pure digital system moving from managing complexity to managing the real world both through wireless connectivity and sensor interfacing. Computational power must be traded for battery power and computational speed is less important since natural processes are often slow.

Another important perspective is technological scaling with strong impact on our design space. Since technology is tailored for digital design, we need to adapt both analog and wireless solutions to cope with the limitations given by digital technology. In fact the rules have changed from an analog design perspective and the low power supply is limiting our design space severely.

With these perspectives in mind there are still a number of design challenges and creative new solutions to silicon system design. In this talk I will discuss some new ways of designing systems in silicon. Analog interfacing, wireless connectivity and even digital computation may be twisted to adapt to advanced technology. I will give real examples of working silicon systems exploring new design strategies and explain how advanced technology is giving us as chip designers new and interesting challenges.

Yoshifumi Nishio received B.E., M.E., and Ph.D. degrees in electrical engineering from Keio University, Yokohama Japan, in 1988, 1990, and 1993, respectively. In 1993, he joined the Department of Electrical and Electronic Engineering at Tokushima University, Tokushima Japan, where he is currently a Professor. From May 2000 he spent a year in the Laboratory of Nonlinear Systems (LANOS) at the Swiss Federal Institute of Technology Lausanne (EPFL) as a Visiting Professor.

Abstract: Solving combinatorial optimization problems is one of the important applications of the neural network (abbr. NN). If we choose connection weights between neurons of the Hopfield NN appropriately according to given problems, we can obtain a good solution by the energy minimization principle. However, the solutions are often trapped into a local minimum and do not reach the global minimum (namely optimal solution). In order to avoid this critical problem, several people proposed the method adding some kinds of noise for solving the problems with the Hopfield NN.

On the other hand, nonlinear systems often produce irregular oscillations even without any external noise. Such oscillations are called "chaos" and are investigated extensively in the past 30 years. Chaos sometimes looks similar to noise but is different in the sense that chaos obeys deterministic equations and hence has a certain level of regularity.

In this talk, I start from the basic of chaos and explain the feature of chaos. Then, some simulation results show that chaos can be exploited to enhance the ability of the neural networks for solving combinatorial optimization problems.

Abstract: This talk will present an editor's personal perspective on writing an excellent paper for technical publication. This talk will first begin with the necessary preparations one would need before one could start actual writing. The talk will then examine briefly the main building blocks of a technical publication. More details and emphasis will be on how to build a convincing case for a technical publication through a series of strategies that may transform a technically correct paper into a compelling one. Step-by-step explanations will be given to illustrate how to compose an excellent paper based on sound technical contents. Finally, this talk will explain some IEEE publication guidelines.

About the speaker : Professor Chang Wen Chen is currently the Editor-in-Chief for IEEE Trans. Circuits and Systems for Video Technology . He has been an Associate Editor for IEEE Trans. Circuits and Systems for Video Technology 1997-2005, an Associate Editor for IEEE Trans. Multimedia 2002-2005, and an Editor for IEEE Multimedia Magazine 2003-2005. He is also on the Editorial Board of J ournal of Visual Communication and Image Representation since 2000. He has served as a Guest Editor for several premier journals, including Proceedings of IEEE and Journal of Selected Areas in Communications. He served as Technical Program Committee Chair for 2006 IEEE International Conference on Multimedia and Expo held in July 2006 in Toronto , Canada and the Technical Program Committee Chair for Visual Communication and Image Processing 2007 held in January 2007 in San Jose , CA . He is serving the General Chair for IEEE Workshop on Signal Processing Systems held in October 2007 in Shanghai , China and Symposium Chair for ICC2008 Symposium on Communication Software and Services held in May 2008 in Beijing , China . His research interests include video coding, processing, analysis, and embedded implementation; reliable and secure image and video transmission over mobile wireless channels; medical image analysis and biomedical information processing; distributed source coding and digital signal processing for communications; and collaborative signal processing and data aggregation for sensor networks. His research has been supported by NSF, DARPA, Air Force, NASA, Whitaker Foundation, and Kodak, Cisco, and Huawei.

He received his BS from University of Science and Technology of China in 1983, MSEE from University of Southern California in 1986, and Ph.D. from University of Illinois at Urbana-Champaign in 1992. Currently he is an Empire Innovation Professor of Computer Science and Engineering at the State University of New York at Buffalo . He was Allen Henry Distinguished Professor at Florida Institute of Technology from 2003 to 2007, and was on the faculty of Electrical and Computer Engineering Department at the University of Missouri-Columbia from 1996 to 2003, and on the faculty of Electrical Engineering Department at the University of Rochester from 1992 to 1996. He also served as the Head of Interactive Media Group at David Sarnoff Research Labs from 2000 to 2002. He is a Fellow of IEEE for his contributions in digital image and video processing, analysis, and communications, and a Fellow of SPIE for his contributions in electronic imaging and visual communications.

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